1. Field of the Invention
The present invention relates to an ink-jet type recording head and a monolithic integrated circuit suitable therefor.
2. Related Background Art
An ink-jet type recording head, which emits droplets of ink by boiling bubbles made of ink, has been widely used for a various kind of recording devices such as printers or video printers which are suitable and well utilized as output terminals for copiers, facsimiles, word processors and host computers.
The recording head of this kind is constructed such that an ink emitting portion having an orifice through which ink is emitted, an electrothermal converter generating thermal energy with which the ink, supplied to the ink emitting portion, is emitted outside, and a driving component for driving the electro-thermal converter are integrally consolidated on the same substrate. A similar kind of the structure was invented by the same inventors of the present application and filed as U.S. Patent Application under the title "Recording Apparatus, Recording Head and Substrate Therefor" on Jul. 31, 1992, bearing Ser. No. 922,870, in which a head is also proposed having the electro-thermal converter which is integrated with logic circuits such as a shift register, a latch circuit, and the like on the same substrate. FIG. 1 illustrates a pattern layout disposed on a substrate 31 of an ink-jet type recording head in accordance with the above mentioned application. An electro-thermal converter 32, which is constituted as an array composed of a plurality of elements, is located along the vicinity of one side of the substrate 31 on grounds that ink is supplied from both surfaces of the one side of the substrate and that the flow resistance can be reduced if the electro-thermal converter 32 is located in the vicinity of an ink supplying room which is usually located near the one side of the substrate 31 to thereby to accomplish high speed accessibility of ink projection.
This high speed accessibility can be further improved if the electro-thermal converter 32 is located within 1,000 .mu.m in length from the side surface of the substrate 31. Further, the closer the electro-thermal converter 32 is located toward the side surface, the more the effect is improved.
There are disposed electric contacts 37, 38, 39 on both surfaces of the substrate 31 at the vicinity of another both sides thereof.
The V.sub.H contact 37 constitutes a contact of a V.sub.H wiring portion 33 which supplies electric energy (pulse) to each of respective electro-thermal converters. The GND contact 38 constitutes a contact of a ground (GND) wiring portion 35 to which the supplied electric energy is grounded. The logic contact 39 constitutes a signal contact of a logic circuit 36 which is composed of a plurality of logic circuits.
There is also disposed a transistor array 34 located between the V.sub.H wiring 33 and the GND wiring portion 35 and connected respectively, each of the electro-thermal converters so as to selectively drive each of the converters. The transistor array 34 is connected such that each of the transistors of the array 34 is controlled by the logic circuit 36.
FIG. 2 shows a cross-sectional view illustrating a part of a monolithic integrated circuit chip in which a heater board is incorporated and which is produced by way of experiment by the inventors of the above described application. There are formed in the same substrate an electro-thermal converter 11, a high voltage proof bipolar NPN transistor 7 which drives the converter 11, and a logic circuit which is constituted by a CMOS circuit composed of PMOS and NMOS transistors. An N.sup.- type epitaxial layer 5 is grown on the surface of a P type silicon substrate 1 in which an N.sup.+ buried diffusion layer 2 is formed.
An NPN bipolar transistor region 7, which is composed of a P.sup.- type diffusion layer 14, a P.sup.+ type diffusion layer 12, and N.sup.+ type diffusion layer 13 and a first layer aluminum wiring 10, is formed in the N.sup.- type epitaxial layer 5.
A P well diffusion layer 4 is formed to isolate each of the composed components electrically in the epitaxial layer 5 so as to be reached a P.sup.+ type buried diffusion layer 3 which is also formed in the substrate 1.
An NMOS transistor region 8, which is composed of an N.sup.+ type diffusion layer 13 serving a source/drain, a gate electrode 15 and the first layer aluminum wiring 10, is formed in the P well diffusion layer 4. The P well diffusion layer 4 is also utilized as an isolation layer which isolates the components from the surface.
A PMOS transistor region 9, which is composed of a P.sup.+ type diffusion layer 12 serving a source/drain, a gate electrode 15 and the first layer aluminum wiring 10, is formed in the N.sup.- type epitaxial layer 5 on the N.sup.+ type buried diffusion layer 2.
In the drawing, a reference numeral 16 denotes an N.sup.+ type diffusion layer; numerals 17, 18 and 19 denote a silicon dioxide (SiO.sub.2) film, an insulating film and an aluminum inter-layer insulating film, respectively; a numeral 20 denotes a second layer aluminum wiring; and numerals 21 and 22 denote a surface passivation film and a tantalum surface passivation film, respectively.
Under the above described structure, the NPN transistor in the region 7 is formed in the relatively thicker epitaxial layer 5 having 8 to 10 .mu.m in thickness in order to maintain high voltage proof against a power source voltage determined by an energy amount supplied to the electro-thermal converter 11.
Accordingly, the P well diffusion layer 4, which serves as an isolation region on the surface of a silicon, must be formed adjacent to the NPN transistor in the region 7 with a relatively large gap therebetween.
As described above, the conventional structure shown in FIG. 2 incorporates the PMOS transistor in the epitaxial growth layer 5 in order to maintain high voltage proof, which requires a wide space region as the region 9 for the PMOS transistor comparing with the region 8 for the NMOS transistor.
FIG. 3 shows an equivalent circuit of the integrated circuit including the portion illustrated in FIG. 2.
A reference numeral 41 denotes an electro-thermal converter array; 42 and 43 a first and a second transistors; 44 a logic gate; 45 a latch logic; 46 a shift register; 47 a heater to V.sub.H connection wiring; 48 a V.sub.H wiring; 49 GND wiring; 50 an enable wiring; 51 a latch wiring; 52 a serial data wiring; and 53 a clock wiring.
The above described structure has, however, following problems which must be solved.
In case of the layout shown in FIG. 2, it is desired to dispose the electro-thermal converter in parallel with the NPN transistor, the logic circuit, the latch circuit and the shift register all of which are used for driving the electro-thermal converter. The layout of the electro-thermal converter elements must be arrayed with a pitch determined depending on a recording density.
The recording density having 360 dpi requires 70.5 .mu.m in pitch.
The NPN transistor, the logic circuit, the latch circuit and the shift register are preferably to be arrayed with the same pitch as that of the electro-thermal converter eelemnts by enhancing a density of the array.
FIG. 4 illustrates a pattern layout disposed on a substrate for a head produced by way of the experiment.
An array density of the electro-thermal converter can be increased by optimizing a shape and a sheet resistance of the converter. However, if the effort is down to cope with the increase of the recording density with an efficiency of inter-layout wiring being maintained high by disposing in a manner described above the electro-thermal converter be in parallel with the logic circuit, the latch circuit and the shift register, array lengths of the logic circuit, the latch circuit and the shift register will be extremely longer than that of the electro-thermal converter resulting in the size of the substrate inevitably becoming larger thereby inhibiting miniaturization of products and increasing the manufacturing cost.